The present invention relates to data processing, and more specifically, to a system for automatic disabling of interrupts upon entry into an interrupt service routine.
In a network controller chip, interrupts to an external central processing unit (CPU) may be produced to direct the CPU""s attention to various interrupt events associated with data transmission and reception. When certain interrupt events are detected, the controller activates its interrupt output to send an interrupt request to the CPU. Upon receiving the interrupt request, the CPU may perform an input/output (I/O) transfer operation to reset the controller""s interrupt output.
However, high-speed communications networks may require a CPU to be interrupted at rates of 20,000-100,000 interrupts per second in response to hundreds various events. As each received interrupt requires the CPU to perform a separate I/O operation to disable the interrupt, substantial CPU""s resources are wasted on interrupt disabling I/O operations.
Thus, in order to increase efficiency of a data communications system, it would be desirable to provide a circuit that automatically disables interrupts upon entry into an interrupt service routine.
Accordingly, the advantage of the present invention is in providing a circuit for automatically disabling interrupts upon entry into an interrupt service routine.
This and other advantages of the present invention are achieved at least in part by providing a data communications device controlled by a CPU and having an interrupt output for producing an interrupt request signal supplied to the CPU. The device comprises an interrupt register for storing interrupt bits representing interrupt events. An interrupt control register stores an interrupt output enable bit to enable the interrupt output when the interrupt output enable bit is in a first logic state, and to disable the interrupt output when the interrupt output enable bit is in a second logic state. An interrupt disabling circuit automatically sets the interrupt output enable bit into the second state when the CPU performs read access to the interrupt register after receiving the interrupt request signal.
The interrupt disabling circuit may be responsive to an interrupt register address signal decoded by an address decoder, and to a read signal indicating that the CPU performs a read operation. For example, an AND gate may be used for receiving the interrupt register address signal and the read signal and producing an interrupt register read signal indicating that the CPU performs read access to the interrupt register. The interrupt register read signal may be supplied to the interrupt control register for setting the interrupt output enable bit into the second state.
When the CPU issues an interrupt enable command, the interrupt output enable bit may be set into the first state to allow the interrupt output to be asserted. When the interrupt output enable bit is set into the second state, the interrupt output is deasserted.
An interrupt generating circuit may be provided for producing an internal interrupt request signal in response to interrupt events. When the interrupt output enable bit is in the second state the internal interrupt request signal is prevented from activating the interrupt output.
In addition to holding the interrupt output enable bit, the interrupt control register may store interrupt event masking bits for preventing the internal interrupt request signal from being produced in response to selected interrupt events.
In accordance with a method of the present invention, the following steps are carried out for automatically disabling interrupts upon entry into an interrupt service routine:
detecting an interrupt event,
asserting an interrupt to a host in response to the interrupt event, and
automatically deasserting the interrupt in response to a read operation performed by the host to read the detected interrupt event.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.